The present invention relates to a technology for exchanging signals between a memory controller and a memory device employed in an information processing apparatus. More particularly, the present invention relates to a memory system for transmitting signals at a high speed to a plurality of memory devices connected to a common transmission line.
In order to implement the IEEE P1596.4 (SyncLink), there has been proposed RamLink, a high-speed memory system employed in an information processing apparatus as disclosed in "SyncLink: A Proposal for an Implementation of IEEE P1596.4 `Ramlink` Optimized for Small (Single-Board) Memory System" by H. Wiggers, Hewlett Packard Company, which was published Mar. 23, 1995, pp 1-6. RamLink is a DRAM system for implementing a transfer speed equal to or higher than 500 Mbytes/s as a bandwidth. Five different topologies have been proposed. As a characteristic of a fourth option among the five proposed topologies, there is provided a system wherein read data is folded in order to reduce the number of skews.
According to this technique, a memory system comprises memory modules 10-0 to 10-7 each incorporating 8 to 9 or 16 to 18 DRAMs (Dynamic Random Access Memories) as shown in FIG. 20. Much like an SDRAM (Synchronous Dynamic Random Access Memory), each DRAM mounted in a memory module has various kinds of timing prescribed with respect to a clock signal. A SDRAM is disclosed in Japanese Patent Laid-open No. Hei5-120114.
The memory modules are arranged in a configuration shown in FIG. 21. As shown in FIG. 21, a memory riser board B0 is erected on a base board BB through a connector C0. Memory modules are provided on the memory riser board B0 in the horizontal direction at fixed intervals.
A memory controller 100 shown in FIG. 20 is provided on the base board BB shown in FIG. 21. The memory modules 10-0 to 10-7 are connected to the memory controller 100 by control lines such as a clock (CLK) line S1, an address (ADR) line S2, a data (DATA) line S3, a CS (Chip Select) line (not shown), a RAS (Row Address Strobe) line (not shown) and a CAS (Column Address Strobe) line (not shown). It should be noted that the address line S3 may include lines for providing command signals such as the chip select line, row address strobe line and the column address strobe line. Accordingly, the address line can be an address/command line.
As shown in FIG. 20, the data line S3 starting from the memory controller 100 is wired to the memory modules 10-0 to 10-7 sequentially one after another before being folded back to the memory controller 100 to form a ring-type bus. Thus, data read out from one of the memory modules 10-0 to 10-7 is propagated to the memory controller 100 through a U-shaped folded path. The wiring and the interface of the data line S3 are the same as a clock line S1 and the address/command line S2 except that only the data line S3 forms a ring-type bus.
With the memory modules 10-0 to 10-7 and the memory controller 100 having a configuration described above, in an operation to write data into the DRAM in one of the memory modules 10-0 to 10-7, a clock signal and the data are supplied to the memory module through the clock line S1 and the data line S3 respectively in addition to an address and a control signal which are fed to the memory module via the address/command line S2.
As described above, the clock line S1, the address/command line S2 and the data line S3 have the same wiring and interfaces so that signals propagated from the memory controller 100 to any of the memory modules 10-0 to 10-7 have the same waveform and an equal propagation time. As a result, the clock signal, the address signal, the control signal and the data signal are supplied to the memory module at the same phase and with the same timing, allowing the data to be written into the DRAM in the desired memory module. Also in an operation to read out data from the DRAM in one of the memory modules 10-0 to 10-7, the data can be taken in by the memory controller 100 with the same timing without regard to which memory module the data is read out from. The technique described above is referred to as a source-clock-synchronized bus system.
In addition, by arranging the memory modules 10-0 to 10-7 on the memory riser board B0 in the horizontal direction at fixed intervals and vertically erecting the memory riser board B0 on the base board BB through the connector C0 as shown in FIG. 21, a plurality of memory modules can be mounted. Furthermore, by vertically erecting the memory riser board B0 on the base board BB through the connector C0, a larger number of memory modules can be provided in comparison with a configuration wherein memory modules are mounted directly on the base board BB.
If there is a limit on the size of a box for accommodating the boards described above, then there is a corresponding limit on a height of the memory riser board B0. As a result, the number of memory modules that can be mounted on the memory riser board B0 is also limited.
Thus, according to the above, when a source-clock-synchronized bus system using a data line S3 is implemented by a piece of memory riser board B0, the number of memory modules 10 that can be connected to a data line (memory bus) is limited by the height limitation. Therefore, the memory capacity per memory bus (memory bank) is limited due to restriction on the height of the memory riser board B0. Here, a memory bank means a memory bus of one source-clock-synchronized bus.
Since the memory controller 100 is connected to the input and output of the data line S3 which is a ring-type bus wired to the memory modules, there is raised a problem that a number of terminals (pins) for the data signal are required. In particular, most of memory controllers are capable of driving a plurality of memory banks. In the case of such a memory controller, a number of terminals (pins) for as many data signals as memory banks are required for controlling the memory banks.
In order to solve the problem of the limited data storage capacity per memory bank described above, in a conventional source-clock-synchronized memory system, the clock line, the address/command line and the data line starting from the memory controller 100 are wired around the memory modules 10-0 to 10-7 mounted on a memory riser board B0 through the connector C0-1 and, then starting from the connector C0-1, further wired around the memory modules 10-8 to 10-15 mounted on another memory riser board B0 through the connector C0-2 as shown in FIG. 21 to form a ring topology with only the data line returning to the memory controller 100. In this way, the data storage capacity per memory bank can be increased. In such a conventional configuration, however, there is raised a problem that, if any of the memory riser boards B0 is pulled out from the base board BB, the connection with its connector C0 is cut off, thereby breaking the ring topology.
Further, by using the configuration described above, the length of the clock line, address/command line and the data line becomes very long thereby increasing the potential for noise on such lines. In addition the flight time of signals on the lines increases the further the memory modules are from the memory controller. This phenomena which particularly affects the data line can serve to reduce synchronization between data signals and address/command signals and reduce the speed of memory access operations. Further, due to this increasing length of the signal lines, noise on the signal lines increases.